Microcontroller and Embedded systems Questions and Scheme of Evaluation
First Internals
1. (a). List the key differences between Microprocessor & Microcontroller
(b). Interpret the concept of Pipeline in ARM Processors with respect to 3, 5 and 6 stages
2. (a). Explain the concept of Combined Cache and Tightly Coupled Memory as part of Core Extension in ARM processors
(b). Compare RISC Processors and CISC Processors by considering appropriate parameters
3. Explain the components of the typical Embedded System Hardware with a neat diagram
4. Summarize the ARM Core data flow model with a neat diagram
5. Classify (only names) the ARM Instructions set and show the operation of the following instructions with the syntax and example
(i). LDR (ii). BL (iii). SMULL (iv). LDMIA
6. Illustrate the operation of Barrel Shifter for the following ARM instructions, write the value at r7 after executing each instruction along with CPSR conditional flag nzcv bit value (i) MOV r7,r5, LSL #2 (Consider r5=0x80000004)
(ii) MOV r7,r5, LSR #2 (Consider r5=0x00000008)
7. Consider a situation where a part of a mathematical relation need to calculate the sum of N natural numbers starting from 10 in solving a complex problem and further to write a computing based logic. Use suitable ARM instructions (like SUBS, Branch and etc.,) to write an ARM Assembly program by considering the initial condition, also note that the resultant sum should be saved in a variable
8. As per the Case Study material shared, Highlight your comparative study points on the adoption ARM7 and ARM9 in Embedded System industry based on their key benefiting factors mentioned in the report to provide better features in an application
Scheme of Evaluation
1a
(1x5)
Marks
|
Microprocessor
|
Microcontroller |
|
It
is only a processor, so memory and I/O components need to be connected
externally |
Micro
Controller has a processor along with internal memory and I/O components. |
|
Cost
of the entire system is high |
Cost of the entire system is
low |
|
Due
to external components, the total power consumption is high. |
As
external components are low, total power consumption is less. |
|
Microprocessor
has a smaller number of registers, so more operations are memory-based. |
Microcontroller
has more register. Hence the programs are easier to write. |
|
It's complex and expensive, with
a large number of instructions to process. |
It's simple and inexpensive with
less number of instructions to process. |
1b. (2+2+1
Marks)
A
pipeline is the mechanism a RISC processor uses to execute instructions. Using
a pipeline speeds up execution by fetching the next instruction while other
instructions are being decoded and executed.
In
the first cycle the core fetches the ADD instruction from memory. In the second
cycle the core fetches the SUB instruction and decodes the ADD instruction. In
the third cycle, both the SUB and ADD instructions are moved along the
pipeline. The ADD instruction is executed, the SUB instruction is decoded, and
the CMP instruction is fetched.
As
the pipeline length increases, the amount of work done at each stage is
reduced, which allows the processor to attain a higher operating frequency.
This in turn increases the performance. The system latency also increases
because it takes more cycles to fill the pipeline before the core can execute
an instruction. The increased pipeline length also means there can be data dependency
between certain stages.
2
2a. (3+2
Marks)
The
cache is a block of fast memory placed between main memory and the core. It
allows for more efficient fetches from some memory types. With a cache the
processor core can run for the majority of the time without having to wait for
data from slow external memory.
ARM has two forms of cache. The first is found attached to the Von
Neumann–style cores. It combines both data and instruction into a single
unified cache.
A cache provides an overall increase in performance but at the
expense of predictable execution. But for real-time systems it is paramount
that code execution is deterministic— the time taken for loading and storing
instructions or data must be predictable. This is achieved using a form of
memory called tightly coupled memory (TCM). TCM is fast SRAM located close to
the core and guarantees the clock cycles required to fetch instructions or
data—critical for real-time algorithms requiring deterministic behaviour. TCMs
appear as memory in the address map and can be accessed as fast memory.
2b (1x5
Marks)
3. (5+5
Marks)
The ARM processor controls the embedded device. An ARM
processor comprises a core (the execution engine that processes instructions
and manipulates data) plus the surrounding components that interface it with a
bus. These components can include memory management and caches.
Controllers coordinate important functional blocks of the system. Two commonly
found controllers are interrupt and memory controllers.
The peripherals provide all the input-output capability
external to the chip and are responsible for the uniqueness of the embedded
device.
A bus is used to communicate between different parts of the
device.
4. (4+6
Marks)
Data enters the processor core through the Data bus. The
data may be an instruction to execute or a data item. The instruction decoder
translates instructions before they are executed. Each instruction executed
belongs to a particular instruction set.
Data items are placed in the register file—a storage bank made up
of 32-bit registers. Since the ARM core is a 32-bit processor, most instructions
treat the registers as holding signed or unsigned 32-bit values. The sign extends
hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they are
read from memory and placed in a register.
ARM instructions typically have two source registers, Rn and
Rm, and a single result or destination register, Rd. Source
operands are read from the register file using the internal buses A and B,
respectively.
The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit)
takes the register values Rn and Rm from the A and B buses and computes a
result. Data processing instructions write the result in Rd directly to the
register file. Load and store instructions use the ALU to generate an address
to be held in the address register and broadcast on the Address bus
After
passing through the functional units, the result in Rd is written back to the
register file using the Result bus. For load and store instructions the
incrementor updates the address register before the core reads or writes the
next register value from or to the next sequential memory location.
5. Data Processing Instructions
Branch
Instructions
Load-Store
Instructions
Software
Interrupt Instruction
Program
Status Register Instructions
Loading
Constants
LDR:
Address accessed by LDR/STR is specified by a base register with an offset
For
word and unsigned byte accesses, offset can be:
An
unsigned 12-bit immediate value (i.e. 0 - 4095 bytes)
LDR
r0, [r1, #8]
A
register, optionally shifted by an immediate value
LDR
r0, [r1, r2]
LDR
r0, [r1, r2, LSL#2]
This
can be either added or subtracted from the base register:
LDR
r0, [r1, #-8]
LDR
r0, [r1, -r2, LSL#2]
BL:
SMULL:
MOV R2,#0xF0000002
MOV R3,#0x00000002
SMULL R0,R1,R2,R3
LDMIA:
7. 5+5
marks
8. AREA
ADDITION, CODE, READONLY ;Syntax
2 + Variable 2 + logic 6 Marks
ENTRY
;MARK FIRST INSTRUCTION TO EXECUTE
MOV
r0, #19 ; STORE INTEGER NUMBER IN R0
MOV
R1,R0
; MOVE THE SAME NUMBER IN R1
ADDIT SUBS r1, r1, #1 ; SUBTRACTION
CMP
r1, #9 ; COMPARISON
BEQ
STOP
ADD
r3,r0,r1 ; ADDITION
MOV
r0,r3 ; RESULT
BNE
ADDIT ; BRANCH TO THE LOOP IF NOT EQUAL
LDR
R4,=RES
STR
R0,[R4]
STOP B STOP
AREA
DATA1,DATA,READWRITE
RES DCD 0X000
END
;MARK END OF FILE
Second Internals
1.a) Write an ARM assembly program to add an array for 16 bit numbers and store the result in a variable Sum.
(b) Show an ARM instruction used to move a 32-bit constant into a register.
2.Illustrate with suitable example the following ARM instructions
(i).SWP (ii).SWI (iii).MSR (iv).LDC 10 M
3.(a) What is an embedded system? List the key differences between general purpose computing system and embedded
system.
(b) Summarize the important features of SRAM and DRAM
4.Illustrate with an example the key purpose(s) of embedded systems in real world.10 M
5.With a neat diagram Explain in detail Seven Segment LED Display Interface used in an embedded system as part of I/O subsystem.10 M
6.With a neat diagram Explain in detail Stepper Motor Interface used in an embedded system as part of I/O subsystem.10 M
PART B
7. Consider a situation where a customer visit a mall and would like to purchase two shirts, the one with a very high price and one with a least price in a lot of 22 shirts price list. Write an ARM assembly logic to help the customer to choose the shirts as per his/her requirement. Also, note that the selected shirt price should be saved in suitable variables.
8. As per the Case Study material shared, differentiate between Sensors and Actuators. Further, as part of analysis of the case study material Justify with suitable example the factors considered in selecting a sensor(s) and actuator(s) for an embedded system like home automation or office security.
Scheme of Evaluation
1a
Syntax 2 Marks code 5 Marks
1b
ADR or LDR instruction 3 Marks
2. Instruction syntax with example (2.5*4) Marks
SWP SWI LDC MSR
3a.
Definition 2 marks
4 differences 4 marks
3b.
4 differences 4 marks
4.
Key purpose explanation with examples (5*2) marks
5. Diagram 3 marks explanation 7 Marks
6. 6. Diagram 3 Marks
Unipolar
3 marks
Bipolar 4 marks
7. syntax and logic 5 marks
area
smallest,code,readonly
entry
start
mov
r5,#7
ldr
r1,=value1
ldr r2,[r1],#4
loop
ldr r4,[r1],#4
cmp r2,r4
bls loop1
mov
r2,r4
loop1
sub r5,r5,#1
cmp
r5,#1
bne loop
ldr r7,=result
str r2,[r7]
stop
b stop
value1
DCD 0x00000003
DCD 0x00000010
DCD 0x00000030
DCD 0x0000003a
DCD 0x00000001
DCD 0x0000005c
DCD 0x00000033
area data1,data,readwrite
result
dcd 0x0
end
syntax
and logic 5 marks
;Program
to find largest ot smallest in an array
AREA LARGEST,CODE,READONLY
ENTRY
START
LDR R1,=VALUE1
MOV R5,#6 ;LENGTH OF REMAINING ARRAY
LDR R2,[R1],#4
LOOP
LDR R4,[R1],#4
CMP R2,R4
BHI LOOP1
MOV R2,R4
LOOP1
SUBS R5,R5,#1
CMP R5,#1
BNE LOOP
LDR R6,=RESULT
STR R2,[R6]
STOP
B STOP
VALUE1
DCD 0X00000004
DCD 0X00000008
DCD 0X00000006
DCD 0X00000009
DCD 0X00000010
DCD 0X00000001
DCD 0X00000007
AREA DATA2,DATA,READWRITE
RESULT
DCD 0X0
END
8. explanation with factors (5+5) marks
Third Internals
1 (5*2) 10 Marks
|
Identify the
key characteristics of Embedded system which makes it Unique compared to
general purpose systems. |
Some
of the important characteristics of an embedded
system
are:
1.
Application and domain specific
2.
Reactive and Real Time
3.
Operates in harsh environments
4.
Distributed
5.
Small size and weight
6.
Power concerns
2 (5+5)
Marks
|
Summarize the
key quality attributes that an embedded system designer considers during the
design process of embedded systems. Explanation |
Operational mode or ‘online’ mode.
1.
Response
2.
Throughput
3.
Reliability
4.
Maintainability
5.
Security
6.
Safety
Non-Operational
Quality Attributes
1.
Testability & Debug-ability
2.
Evolvability
3.
Portability
4.
Time to prototype and market
5.
Per unit and total cost
3. diagram + explanation (4+6)
Actuator part Sensor part: Control part: Sensor data Control unit: User feedback:
Integrated
control panel:
I/O
interface:
4.
Diagram + explanation (4+6)
High
speed Electronic Control Units (HECUs)
Low
speed Electronic Control Units (LECUs)
Automotive
applications use: serial buses for
communication.
Controller
Area Network (CAN):
Local
Interconnect Network (LIN):
Media Oriented System Transport (MOST)
Key
Players
5. Distinguish between Threads and Process in connection with RTOS. 5 Marks
Highlight any two services offered by Real Time Kernel in RTOS.
Explanation of any 2 services
6. Distinguish between Multitasking and Multiprocessing with regards to RTOS.5Marks
. The execution of more than one task simultaneously is known
as multitasking. The availability
of more than one processor per system, that can execute several set of
instructions in parallel is known as multiprocessing.
|
6. Distinguish between Multitasking and Multiprocessing with regards to RTOS.5Marks . The execution of more than one task simultaneously is
known as multitasking. The
availability of more than one processor per system, that can execute several
set of instructions in parallel is known as multiprocessing. 2. The number of CPU is one. The
number of CPU is more than one. 3. It takes moderate amount of time. It takes less time for job processing. 4. In this, one by one job is being executed at a time. In this, more than one process can be
executed at a time. 5. It is economical. It
is economical. 6. The number of users is more than one. The number of users is can be one or more than one. 7. Throughput is moderate. Throughput
is maximum. 8. Its efficiency is moderate. Its
efficiency is maximum. |
7.
|
Consider a
situation where the prices of Ten Cloths have been stored in continuous
memory locations from lowest to highest. Write ARM assembly logic to store
the price from highest to lowest in the same memory locations. |
AREA STACK,CODE,READONLY
ENTRY
START
MOV R5,#6 ; INTIALISE COUNTER TO
6(i.e. N=6)
MOV R6,#6 ; INTIALISE COUNTER TO
6(i.e. N=6)
MOV R7,#6 ; INTIALISE COUNTER TO
6(i.e. N=6)
LDR R3,=REV ; LOADS THE ADDRESS OF
FIRST VALUE
MOV R9,#1
;
Following code to initilize the memory locations
INIT
STR R9,[R3],#4
SUBS R7,R7,#1 ; DECREMENT COUNTER
ADD R9,R9,#1
CMP R7,#0
BNE INIT ; LOOK BACK TILL ARRAY ENDS
LDR R1,=REV ; LOADS THE ADDRESS OF
FIRST VALUE
;
Following code to push array values to stack memory
LOOP
LDR R2,[R1],#4
STMFD R13!, {R2}
SUBS R5,R5,#1 ; DECREMENT COUNTER
CMP R5,#0
BNE LOOP ; LOOK BACK TILL ARRAY ENDS
LDR R3,=REV ; LOADS THE ADDRESS OF
FIRST VALUE
;Following
code to pop item from stack and store it in the array
LOOP1
LDMFD R13!,{R4}
STR R4,[R3],#4 ; STORES THE RESULT
IN R1
SUBS R6,R6,#1 ; DECREMENT COUNTER
CMP R6,#0
BNE LOOP1 ; LOOK BACK TILL ARRAY
ENDS
LDR R3,=REV ; LOADS THE ADDRESS OF
FIRST VALUE
;Following code is to verify the values
MOV R7,#6 ; INTIALISE COUNTER TO 6(i.e. N=6)
LOOP2
LDR R5,[R3],#4 ; STORES THE RESULT IN R1
SUBS R7,R7,#1 ; DECREMENT COUNTER
CMP R7,#0
BNE LOOP2 ; LOOK BACK TILL ARRAY
ENDS
STOP
B STOP
AREA DATA1,DATA,READWRITE
REV
DCD 0X00, 0X00, 0X00, 0X00, 0X00, 0X00
END
8.
|
As per the Case
Study material shared, highlight the key features of Linux RTOS
with respect to Memory Management, Process Management and Network Support
with a neat diagram. Further, draw the Inferences on the
characteristics of any three RTOS with respect to IDE support, Support for
CPU, Support for Real time, Memory, and GUI Support. |
Key
Features Linux RTOS
3+3
Marks
Memory
Management, Process Management and Network Support
Diagram
4Marks
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